On-the-fly printer with shortened print cycle

ABSTRACT

An &#39;&#39;&#39;&#39;on-the-fly&#39;&#39;&#39;&#39; printer is equipped with an associative memory which is arranged to automatically account for all the nonprintable characters in a print line and to shorten the print cycle time of the printer.

United States Patent 1191 Mahoney 1 Aug. 6, 1974 ON-THE-FLY PRINTER WITHSHORTENED I 3,303,776 2/1967 Rausch 101/93 c PRINT CYCLE 3,656,4274/1972 Foley i .1 101/93 C 3,681,760 8/1972 Salava i 1 .1 340/1725 [75]Inventor: Ralph W- Ma n y, Telford, Pa. 3,697,958 10/1972 Laren 340/17253,701,991 10/1972 L'k 11 101/93 CX [73] Ass'gnw i f 'f New 3,760,366 91073 GI'EZQOETY. 340/1725 [22] Filed: Sept' 12! 1973 PrimaryExaminer-Robert E. Pulfrey 2 App] 39 3 Assistant Examiner-Edward M.Coven Attorney, Agent, or FirmCharles C. English [52] 1.1.8. Cl. 101/93C, 340/1725 [51] Int. Cl. B4lj 7/08, G06f 3/12 [57] ABSTRACT [58] Fieldof Search 101/93 C; 340/1725; ,9

235/61 P A11 on-the-fly prmter 1s equipped wlth an assoclative memorywhich is arranged to automatically ac- [56] Reerences Cited count forall the non-printable characters in a print UNTED STATES PATENTS lineand to shorten the print cycle time of the printer.

3,289,576 l2/l966 Bloom et al 1. 101/93 C 9 Claims, 7 Drawing Figures qso 301 IF? 2113515 MEM. LOCATIONS 0-63 I I SELECY ADDRESS 1 D l rgmmhi's 700 CHIPS 31,12,311 3O T3 -31O 21 670 L 0 }r0 cums -680 F31,32,33

1332mm I I 82 T.

TO CHIPS '*l FF F'F' "'5 T2 223: c1.. 1 SET CL. 1 SET 26 rem/1mm:COUNTER 48b 491: m T 'T 64 equal DATA Icr W 63 65 66 W5 39o 1 420 TM TF4n SP 480 49a 52 TF3 2 -1 -F i .J217 :F 93 39 842 62 3?, s zt 48 49 27TF2 't'lfi '8 "'7 w t 5 T0 CHIPS t3; 3|, 32, 33 2 BUS 22 PATENIEUIUB61974 SHEEI 1 OF 5 mmooomo EmE Mi Mwfimmmw mommmuomm 225182 M68 55;:3526 IMPZEQ 26x6 mm PATENIED 51974 SHEEI 2 IF 5 mm mam non 0m nOm om Owmm mm mm mmm m mZOFdOOJ 552 mm mm com 2m ON-THE-FLY PRINTER WITHSHORTENED PRINT CYCLE BACKGROUND This invention relates to an on-the-flyhigh speed printer for use with automatic digital computer systems andin more particular to an improved means for shortening the print cycletime of such printers.

The oscillating bar printer described in US. Pat. No. 3,282,205 or themoving band printers described in U.S. Pat. Nos. 3,303,776 and 3,289,576are examples of the different classes of on-the-fly printers with whichthe present invention is concerned. Rotating drum printers, now wellknown to the art, are also illustrative of another class of on-the-flyprinters with which the present invention is concerned.

In general, an on-the-fly printer is comprised of two basic components;namely, an electro-mechanical print mechanism and an electronic controlsection therefor. The print mechanism includes a constantly moving typecarrier; a plurality of print hammers; and means for guiding and feedinga print record medium between the hammers and the type carrier. The typecarrier which may be a chain, a band, a bar or a drum has a plurality ofdifferent type characters so located thereon as to form at least onecomplete character set. The character set is arranged on the carrier sothat as the carrier is moved one or more complete character setssequence past each hammer during the print cycle. Generally a separateprint hammer is provided for each print column and each of the hammersis actuated when the type character aligned therewith corresponds to thecharacter to be printed in that particular print column.

The electronic control section usually includes, a line buffer memoryfor storing a line of data to be printed; a code generator synchronizedwith the movement of the type carrier to identify the type characterscoming into printing position; and a comparison circuit for comparingthe type characters coming into printing position with the datacharacters stored in the print line buffer memory. Whenever thecomparison circuit indicates that the type character coming into aprinting position in a print column corresponds to the data character tobe printed in that column, the corresponding print hammer is actuatedand the character is printed. After all of the columns have been printedthe printer electronic section generates a print end" signal which maybe fed back to the data source to request the next line of data to beprinted.

One common method of generating the print-end signal is to use a countercircuit or the like which counts the number of equal comparisonsgenerated by the comparison circuit and when this count reaches apredetermined value the print-end signal is generated. A shortcomingwith this mode of operation is that the printing rate or the print cycletime remains fixed even though the ratio of printable to non-printablecharacters in a line of data may vary. In more particular, the line ofdata stored in the print line buffer memory may frequently include datacharacters which are not part of the character set contained on the typecarrier. In this case, those characters which are not on the typecarrier are, of course, non-printable and an equal comparison will notresult. As a consequence, the electronic section of the printer willcontain means for generating a print ending signal after it has beenestablished that all the different type characters of a complete sethave sequenced past each of the print hammers. This action requiresaminimum fixed period of time.

To avoid the fixed cycle print rate limitations the prior art (US. Pat.No. 3,289,576) has suggested the use of a print cycle control memoryplane. The print cycle control memory plane parallels the print linebuffer memory which is addressed synchronously with the print linebuffer memory.

Initially, each memory location in the print cycle control memory planeis set to its zero state. During the time that data is being read intothe print line buffer memory, each location in the print control cyclememory corresponding to those locations in the print line buffer memorystoring a printable character is set to a binary one'. Blanks or othertypes of non-printable characters loaded into the print line buffermemory are identified and prevent the setting of the correspondinglocations in the print cycle control memory to their one state. Thus, atthe end of a read in cycle every printable character stored in the printline buffer memory is represented by a one stored in the correspondingprint cycle control memory location.

During read out, the memory locations in the print cycle control memoryare switched to their zero state for each equal signal comparison fromthe comparison circuit. Finally, when all of the locations in the printcycle control memory have been switched back to zero it is known thatall of the printable characters have been optioned for printing and theprinting of a line of data should have been completed.

The disadvantages of the above prior art approach are that a special noprint" signal must be generated by the program or by providing specialhard wired decode circuits for each non-printable character. Moreover,the entire process of clearing the print cycle control memory andsetting up the one states in the appropriate memory locations of theprint cycle control memory must be repeated for each line of data storedin the line buffer.

SUMMARY OF INVENTION The present invention resides in the electroniccontrol section for an on-the-fly high speed printer. The controlsection is conventional in organization except that it includes anassociative memory which is used to automatically step the comparisoncounter for each non-printable character received by the print linebuffer memory. The associative memory of this invention has as manystorage locations as there are possible binary code combinationsutilized by the printer system. For example, if an eight bit binary codeis utilized by the system, the associative memory will contain 256storage locations.

Initially, during the start up of the printer, all of the memorylocations in the associative memory are set to a first state. Then thecode combinations used to represent the character set contained on thetype carrier are sequentially fed to the associative memory as memoryaddress signals. Each distinct code combination addresses a differentlocation in the associative memory, and as it does so it causes theaddressed location to be set to a second state. At the end of thisoperation, the memory locations in the associative memory whichcorrespond to the complete character set contained on the type carrierare all set to a second state while the memory locations which have nocorrespondence to the character set (non-printables) all remain set totheir first state. After the associative memory has been set up as abovedescribed, the printer is ready to go into its print mode. During thisphase of operation, the data bytes forming a line to be printed, aretransmitted from the data source to the print line buffer where they arestored. As these characters are being stored they are also used toautomatically address the associative memcry and read out the state ofthe addressed location. Those locations which are in their first state(non printable) generate a stepping signal which is sent to thecomparison equal counter to step this counter once for eachnon-printable character being stored in the print line buffer. In thisway at the end of the data input cycle before printing has started thecomparison equal counter has taken into account all the non-printablescontained in the print line. Thus when printing actually starts only theprintable characters need be counted before a print-end signal isgenerated. Consequently, the print cycle time is not fixed since theprinting can be terminated and the next line of data requested as soonas all the printable characters have been printed.

It is accordingly an object of the present invention to provide anautomatic control over the print cycle time of an on-the-fly printer.

It is another object of the present invention to provide a simple meansfor automatically controlling the print cycle time of a large class ofon-the-fly printers.

These and other objects and features of the present invention willbecome apparent upon a careful consideration of the following detaileddescription when taken together with the accompanying drawings wherein:

FIG. I is a highly simplified block diagram of a typical on-the-flyprinter system showing the incorporation of my invention therein;

FIG. 2 is a simplified diagram showing the addressing scheme, duringread out, for the associative memory;

FIGS. 3, 4 and 5 taken collectively show in somewhat more detail theaddressing and controls for the associative memory;

FIG. 6 is a block illustration of a timing pulse generator useable bythe present invention; and

FIG. 60 comprises a set of timing diagrams useful in explaining theoperation of FIG. 6.

Reference is now made to FIG. I. In this figure the block 10 representsthe central processor of a computing system. The central processor 10 isof conventional design and includes within its organization a suitableinput/output channel. Connected to the input/output channel is a databus 24 and a set of control cables 25. The data bus in the presentexample includes eight parallel signal lines over which the 8 binarybits of an 8 bit character byte is applied to the main printer controlcircuits II which is also of conventional design. The printer controlcircuits ll typically include a data output register for storing a byteof data delivered thereto from the central processor 10, and a controlregister for storing command signals also delivered thereto by thecentral processor over the data bus 24. The printer control logic 11further includes a decoder network connected to the control register fordecoding the commands stored therein and for delivering suitable controlsignals to the rest of the printer. Further circuits typically includedin the printer control logic 11 are: counters for counting data bytescomprising a line of print, or for counting and controlling certainoperations in the system, a clock source for providing timing signalsused in timing the operation of the printer; and a number of controlflip-flops for producing various control signals which are also used bythe printer.

The block labelled 12 is the print line buffer memory for the printerand as shown it is understood to be a non-destructive memory whichincludes the usual read/write control and memory addressing circuits.The print line buffer 12 is used to store the line of data characters tobe printed and thus contains as many character storage locations asthere are columns of print utilized by the printer. Each location of theprint line buffer is capable of storing one 8 bit character byte whichis transmitted thereto from the output data register of the controlcircuits 11 via an eight line cable designated 22.

The block 14 represents a code buffer memory which as shown isunderstood to be a non destructive read out memory which includes theusual memory addressing and read/write control circuits therefor. Thepurpose of this buffer memory is to store the binary coded signalsrepresenting each of the printable characters carried on the typecarrier of the printer mechanism 21. Thus, code buffer memory 14 willcontain at least as many 8 bit character memor locations as there aredifferent type characters in the character set on the type carrier. Inpractice, and particularly with band printers one complete typecharacter set may be repeated several times on the band in order toincrease the printing rate of the printer. For example, a 48 characterset may be repeated as many as eight times on the band. In this case thecode buffer may have as many as 384 locations, one set of 48 locationsfor each character set on the band, and each set of 48 locations storesthe codes for the characters making up the character set contained onthe type carrier. The code buffer 14 like the print line buffer 12 isconnected to the output data register of the printer control circuits 11via the data bus 22.

Connected to the outputs of the print buffer memory 12 and the codebuffer 14 is the comparator circuit 16. The comparator circuit 16 has afirst set of eight input terminals connected to the 8 bit output of theprint line buffer 12 via cable and a second set of eight input terminalsconnected to the 8 bit output of the code buffer 14 via cable 14a. Inoperation, the comparator compares the coded output from line buffer 12against the output from code buffer I4 and whenever the character codessimultaneously being read from these memories are the same, thecomparator l6 develops an output signal on line 17.

Further included in the printer illustrated in FIG. I is the printmechanism 21 itself. This mechanism, it will be understood, includes thetype character carrier; a set of print hammers, (usually one for eachcolumn of print); and a ribbon and paper guide and feeding mechanism.Also included in the printer system is a comparison equal counter 19which is connected to receive and count the outputs of the comparatorl7. Initially the counter 19 is set during the print cycle to a countcorresponding to the maximum number of columns of print. Then thecounter 19 is decremented by one each time the comparator 16 produces anoutput. A decoder network is connected to the output of the counter 19and detects when the counter has been decremented to zero. When thiscondition is obtained, the decoder 20 sends a print-end signal to thecontrol circuits 11 via path 15.

The foregoing described structure is conventional and its operation isas follows. During system start up, the central processor 10 issues an 8bit load command over the data bus 24 to the printer control 11. At thistime the central processor energizes one of the control lines 25 toindicate to the printer control 11 that a command is being transmitted.The printer control 11 senses the signal on the control line 25 andgates the load command into its control register. The decoder associatedwith the control register decodes the load command and causes thecontrol line 26 to be energized which in turn places the code buffer 14in a write mode. Thereafter, the processor 10 sends a set of codecharacters to the code buffer memory 14 via bus 24, control circuits 1]and bus 22. The code character set transmitted to the code buffer 14correspond to the type character set contained on the type carrier ofthe printer mechanism 21 and the transmission is serial one character ata time. As each character is transmitted one of the control lines 25 isenergized to cause the characters to be gated into the output dataregister of the control circuits 11 and then into the code buffer 14.During this period of time the memory addressing circuits within thecode buffer memory 14 are made operative to place the successivelyreceived code characters in successive address locations of the memory14. When the loading operation is completed, the printer control logicll energizes one of the control lines 25 to signal the central processor10 that the loading process has been completed and is ready to acceptthe next command. The next command in this case is a print command, andit is stored in the control register of the print control circuit I] anddecoded to energize the print command line 27. Energizing the printcommand line 27 places the print buffer 12 in a write mode. Thereafterthe processor 10 transmits a complete line of data characters to beprinted over bus 24 to the Print Line Buffer 12 via the output dataregister in control circuits 1] and the bus 22. This transmission takesplace one character at a time with the successively received charactersbeing stored in successive memory locations of the print line buffer 12.After the complete line of print characters have been stored in buffer12 (this fact may typically be indicated by a line character counter inthe print control circuits 11 or the processor 10) the control circuit11 develops a printing signal on the control line 28. The printingcontrol signal appearing on line 28 together with an index pulsedeveloped by printer mechanism 21 and appearing on line 29 are appliedto the print and code buffers 12 and 14. The index pulse appearing online 29 is generated each time a new group of type characters on thetype carrier comes into printing position. The index pulse appearing online 29 together with the printing signal appearing on line 28 cause thememories 12 and 14 to pass thorugh a read out cycle where the code foreach type character on the band then in printing position is read out ofcode buffer 14 and the characters to be printed in these positions isread out of memory 12. The read out cycle is repeated for each indexpulse appearing on line 29 and usually continues until all of thedifferent type characters of a character set have sequenced past each ofthe print hammers. As the code and print characters are read out of thememories 14 and 12 respectively they are applied over buses 14a and 12ato the comparator 16 where they are compared. Each time these charactersproduce a match, a signal pulse is produced on line 17. The printingsignal then present on line 28 opens the AND gate 18 to permit thecompare signal to be applied to the print hammers contained in theprinter mechanism 21. The printer mechanism 21 contains in addition tothe aforedescribed components, a print actuator matrix which switchesthe output from gate 18 to the proper print column actuator. At the sametime, the compare output signal from gate 18 is also applied through the0R gate 23 to decrement the count stored in counter 19. Counter 19 isinitially set in response to the print signal appearing on line 27, atthe start of a print cycle, to a count which represents the maximumnumber of columns of print. After the counter has been decremented tozero, the decoder 20 detects this event and sends a signal back to theprinter control circuits 11 via path 15. The control circuits ll sensethe signal on path 15 and generates in response thereto a request forthe next line of data or in the alternative terrninates the printeroperation.

The aforedescribed structure and operation is conventional. Thedeparture provided by the present invention lies in the incorporation ofan associative memory 13 in the above-described structure. Theassociative memory has as many memory locations as there are possiblebinary codes in the multi-bit code em ployed by the printer. Forexample, in the present case where an 8 bit code is assumed, theassociative memory has 256 memory locations and each location is capableof storing 1 binary bit. The associative memory also includes a set ofaddress lines which when activated will access any of the 256 memorylocations in accordance with the binary coded signal applied to theaddress lines. These address lines are connected to the output bus 22 ofthe data output register of the printer control circuits 11 so that eachcharacter appearing on the output data bus 22 will automatically accessa corresponding location in the associative memory.

in operation and in response to the load command signal appearing online 26, a circuit within the memory 13, as will be describedhereinafter, operates initially to clear all of the memory locations inmemory 13 to zero". After the clearing operation, the memory 13 isplaced in a write mode so that as each code byte is loaded into the codebuffer 14 it will also address the memory 13 via bus 22 and store a onein the addressed location. Thus at the end of the load operation whenthe code buffer 14 has stored all the incoming code bytes, the memorylocations in the memory 13 corresponding to these code bytes will all beset to one. The rest of the memory locations in memory 13 will remainset to their zero state.

Following this operation the printer is placed in a print mode and aprint control signal is developed on line 27 as previously indicated.When the printer is placed in a print mode and while the print buffer 12is being filled with a line of data, the print signal on line 27 placesthe associative memory 13 in a read mode. Then as the bytes of datacomprising the line to be printed are received and are stored in theprint buffer 12 they are also applied via bus 22 to the address lines ofthe associative memory 13. Each data byte being stored in memory 13 thuscauses a read out of the memory location it addresses in memory 13. Ifthe addressed memory location stores a one the signal output from theassociative memory 13 has a first level, while if the addressed locationstores a zero the associative memory produces a read out signal of asecond level. The second level or zero output signals of the memory 13is applied to the decrementing input of counter 19 via line 23a and theOR gate 23. Thus while the print buffer 12 is being loaded and before aprinting operation occurs, all the non-printable characters, which arethose addressed locations having a binary zero stored therein are usedto decrement the counter 19. As a consequence, at the end of the cyclewhere the print buffer is being loaded with a line of data, the counter19 will be decremented to a count which equals the number of printablecharacters which are stored in the print buffer 12. Then as printingproceeds the counter 19 will be further decremented via gate 18 and ORgate 23 to zero as soon as all of the printable characters stored inbuffer 12 have been made available for printmg.

From the foregoing it will be apparent that a feature of the presentinvention is that with a conventional load command where each printablecharacter is being stored in buffer 14 the associative memory issimultaneously and automatically being set to distinguish betweenprintables and non-printables without further program intervention. Alsothat during the execution of a print command where the buffer memory I2is being filled all the non-printable characters are accounted forautomatically.

It will be further apparent that the load command, which functions tosimultaneously load the code buffer 14 and set the associative memory13, need be executed only once during the printer start up and thenthereafter the associative memory will automatically distinguish betweenprintable and non-printables for each successive line of print data.Moreover, if it becomes desirable to change the code used by the systema new load command will automatically set the associa tive memory torecognize the new code without further intervention.

Before discussing the associative memory in detail, a discussion of thismemory and its organization during read out will now be made inconnection with the simplified illustration of FIG. 2 to which referenceis now made. As herein illustrated, the memory is made up of fourIntegrated Circuit Chips 30, 31, 32 and 33 each of which are stock itemsmade by lntersil and others. For example, the Integrated Circuit Chipdesignated No. IM55OI made by Intersil Corporation of Cupertino, Calif.is suitable for the present application. Each chip contains the facilityfor storing l6 4-bit words and thus four such chips can be used to store256 bits or I bit for each of the 256 code combinations possible with an8 bit signal byte. Each of the chips has a 4 bit address section with abuilt in decoding circuit arranged so that energization of the 4 bitaddress input will select one of the l6 4-bit words for reading orwriting. The four bit address terminals for chip 30 are shown at 30a,30b, 30c and 30d and it will be understood that the other chips 31, 32and 33 have similar address inputs. Each of the chips also furthercontains a 4 bit output section shown at 30e, 30f, 30g and 30h for chip30; at 3le to 31h for chip 31 and so on. These outputs are arranged sothat on readout the 4 bits (MSB to LSB) of a selected word appearsimultaneously on the respective e to )1 terminals of the selected chip.All of the chips also contain, but not shown in this figure, a 4 bitdata input section for feeding input signals into the chip during awrite operation and a write enable terminal which when held at a firstpotential level permits nondestructive readout from the chip and whenheld at a second potential level permits writing. The write enableterminals of the chips are normally all held at their read out potentiallevel except during a write operation. Finally, each chip has a chipselect terminal 35 to 38 which has to be energized to render, the input,the output, and the addressing circuits of the chip active.

The addressing information for the memory appears on the eight line bus22 connected to the output data register in the control circuits 11.This bus has the code characters applied thereto during the load commandand the print data characters during the print command. In each instancethe coded characters can be thought of, insofar as the associativememory is concerned, as having the following format:

Bit Position Format In this format the least significant two bits BB areused to select one of the 4 bits of a word, the 4 middle bits 3 to 6(WWWW) select one of the sixteen words of a chip and the two mostsignificant bits 7 and 8 (CC) are used to select one of the four chips.For example, it will be seen from FIG. 2 that when the 2 CC bits are0-0, chip select gate 39 connected to the number 7 and 8 bit linesresponds to energize the chip select terminal 35 associated with chip30. Chip 30 is thus selected for reading or writing when gate 39 isactive. The small circles at the base of gate 39 and the other gates,indicates a signal inverting action on the corresponding inputs to thegate. Thus, when the number 8 and 7 bits correspond respectively to O-lthe chip selector gate 40 responds to energize the select terminal 36 toselect chip 3]. Finally, from the connections shown in FIG. 2, a 1-0condition and a l-l condition respectively for the number 8 and 7 bitswill select chips 32 and 33 respectively. The four gates 39 to 42 takencollectively thus form a decoding network for chip selection.

Returning to the output section of the chips 30 to 33, it will be seenthat the corresponding output bit lines from each of the chips arebuffed together via a respective one of four OR gates. Only the first(MSB) and fourth (LSB) of the OR gates are shown at 43 and 44respectively. The output of each of these four OR gates serves as oneinput to a respective AND gate; only the first and fourth of which areshown at 45 and 46. The second input to each of the four AND gates is inturn derived from the four outputs of a decoder which comprises a fourAND gate matrix only the first and fourth gates of which are shown at 48and 49 in the drawings. These latter gates are connected to the 1st and2nd bit lines of bus 22 so that each of the four gates represented by 48and 49 is opened by a different signal input combination on lines 1 and2 of bus 22. For example, when the input signal combination on lines 1and 2 are both zero gate 49 is opened which in turn renders gate 46operative. Similarly, when the input signal combination to gate 48 isl-l, gate 48 is open which in turn renders gate 45 operative. While notshown the other two gates of the decoding matrix connected to lines 1and 2 of bus 22 operate to respond to the 10 and the signal combinationsto in turn open up the two intermediate output gates (not shown) betweengates 45 and 46. Finally, the outputs from all four of the output gatesrepresented by gates 45 and 46 are buffed together by the OR gate 47 toform common output line 50 for the memory.

From the foregoing it will be recognized that, during read out, animcoming coded signal byte appearing on bus 22 and ranging from 00000000to 001111 11 will address one of the 64 bit locations in chip 30; anincoming coded signal byte ranging between 01000000 and GI l l l l llwill address one of the 64 bit locations in chip 31; an incoming codedsignal byte ranging from 10000000 and lOl l l l l 1 will address one ofthe 64 bit locations in chip 32; and finally, an incoming coded signalbyte ranging from I 1000000 and l l l l l 1 l 1 will address one of the64 bit locations in chip 33. For example, assume the incoming codedsignal byte to be 101 l 11 l l CCWWWWBB It will be seen that in thisbyte, the CC bits are decoded by gates 39 to 42 to select chip 32 whichcontains storage locations 128 to 19]. The WWWW bits are internallydecoded by the chip 32 to select the 16th 4 bit word in chip 32, and theBB digits are decoded by the four gates represented at 48 and 49 toselect gate 45, the MSH bit position of the 16th word in chip 32.

Reference will presently be made to FIGS. 3, 4 and 5 for a more detaileddescription of the operation of the associative memory 13 during bothreading and writing. Before such description proceeds, however,reference will now be made to FIGS. 6 and 6a which show a representativetiming pulse generator usable, for example, in the control circuits 11for timing the operation of the printer. As illustrated, the timingpulse generator is of the recirculating type and includes a delay line51 which has an input terminal 53 connected thereto, and a recirculationpath 54 in which a shaping amplifier 52 is included. In operation, asingle short duration pulse applied to the input terminal 53 propagatesdown the delay line 51 to its output terminal where it is returned tothe input terminal 53 through the reshaping amplifier 52 and thefeedback path 54. With this interconnection the single input pulsecontinuously recirculates through the delay line 51. The delay line inturn contains a series of generally equally spaced tap points indicatedin the figure as TP-l through TP-6 arranged so that the recirculatingpulse appears sequentially at the respective tap points during itspropagation through the delay line 5]. This action will thus generate arecurrent series of pulses, such as illustrated in FIG. 6a, at each ofthe tap points TP-I through TP-6. As shown in FIG. 6a a pulse willappear at each of the tap points during each recirculation cycle withthe pulses appearing at successive tap points being predeterminedlydelayed from one another. In a typical embodiment the generated pulsesmight be, for example, I50 nanoseconds in duration and the time delaybetween the successive tap point pulses TP-l to TP-2, TP-2 to TP-3, etc.set at 200 nanoseconds.

Reference will now be made to FIGS. 3, 4 and 5. In connection with thesefigures it should be noted that the illustration given therein has beensimplified by showing only one of the integrated circuit chips 30 fromFIG. 2. It is believed, however, that the manner in which the remainingthree integrated circuit chips 31 through 33 are incorporated in thisstructure will be obvious.

In the following description, the operation of the associative memorywill be set forth in two phases. The first phase will cover the writeoperation which occurs during the load command and the second phase willcover the read operation of the memory which occurs during the printcommand. From the previous description it will be recalled that thefirst step in a write operation (load command) is the clearing of alllocations of the memory to binary zero. A clear flip-flop 56, FIG. 4, isadded for this purpose. The clear flip-flop 56, together with a loadflip-flop 57 and a data request flipflop 58 comprise the basic controlsfor the memory 13. Initially it is assumed that all of these flip-flopsare in their cleared condition and that their respective output linesare thus inactive. The output 60 of the load flipflop 57 is connected toa set control gate 59 for the clear flip-flop. The load flip-flop in itscleared condition and with its output line 60 inactive partiallyconditions the set input gate 59 of the clear flip-flop 56 as isindicated by the small inverter circle at the base of the gate 59. Thesecond input to gate 59 is derived from the control line 26 of thecontrol circuits II and this line is activated when the load command isgiven. Thus during a load operation line 26 is rendered active and gate59 is opened to gate a TP-l timing pulse to the set input terminal ofthe clear flip-flop 56. When the clear flipflop 56 is set the clearoutput, terminal A, of the flipflop 56 is rendered active. The output ofthe clear flipflop at terminal A is applied (FIG. 5) in parallel viafour OR gates to the chip select terminals 35 to 38 of all four chips3033. Only the first 39a and last one 42a of the four OR gates are shownin the FIG. 5. The output of each of these OR gates 39a to 42a isapplied to the respective select terminals 35 to 38 of all four chipsthereby rendering all chips active.

The clear output, terminal A, of flip-flop 56 is also used via line 62to jam the data inputs to each of the memory chips 3033 to zero at thistime. Each chip (3033) has its own set of data inputs which comprise aset of four flip-flops. Only the first and last data input FF for chip30 are shown in FIG. 5 at 67 and 68. Flipflop 67 is the M58 input whileflip-flop 68 represents the LS8 flip-flop. As indicated, the data inputflip-flops for each chip are set to zero or their cleared condition bythe clear signal which appears on line 62 and is applied to the clearinput of each of the data input flipflops via a set of OR gates only thefirst and last of which for chip 30 are shown at 65 and 66. Thus whenthe clear signal is applied to line 62 and thence through the respectiveOR gates represented by 65 and 66 it jams all four data input flip-flopsfor each chip to zero. In this condition, each of the data input linesto all of the chips is inactive or at a zero condition. The data inputlines for the M88 and LSB positions for chip 30 are shown at 670 and68a. When the clear signal first appears on line 62 it energizes asingle pulser circuit 63 which send a momentary pulse out on its outputline 64 to the clear terminal (CL) of a four stage, scale of 16 counter55 clearing this counter to its zero state. The counter 55 is a standardintegrated circuit chip which has a clear terminal labelled CL, a loadterminal labelled LD, a counter terminal labelled CT and a set of fourdata input temiinals labelled DATA. A circuit such as that designated SN74 l 93 sold by Texas Instruments Inc. of Dallas, Tex. and described incatalog CC 41 1 published l973 is representative of such a countercircuit. In operation when a pulse is applied to the clear terminal CLvia lead 64 it clears the counter to zero while the activated clear line62 operating on the load terminal LD renders the data input circuit ofthe counter inactive but the count terminal CT active. At this time thetiming pulses TP-2, TP-4 and TP-6 are applied through OR gate 69 to thecount terminal CT to sequence the counter through its 16 states. As itdoes so the output of the four stages of the counter are applied inparallel to the address lines of the four chips 30-33 so that as thecounter is sequenced through its 16 states each of the l6 words of theassociated chips will be addressed in sequence. The address lines forchip 30 are shown in FIG. 5 at 30a to 30d. Simultaneously with theaddressing of the 16 words in each chip, the write enable termianllabelled WE of each of the chips 30, 31 32 and 33 is energized from theoutput of an OR gate 70 which receives the output of an AND gate 71. Thelatter gate has as its two inputs, the clear output of the clearflip-flop 56 as indicated by the terminal A and the further output fromOR gate 72 which receives the TP-l, TP-3 and TP-S timing pulse signals.Thus as the counter 55 is sequenced through its 16 states addressing the16 words in each of the chips in succession, the timing pulses TP-l,TP-3 and TP-S which are applied to the write enable terminals WE causebinary zeros to be written in each of the four bit positions of each ofthe l6 words. When the counter reaches its l6th count, (1 l l l theoutput of the counter 55 is decoded in an AND gate 73 to produce anoutput signal on terminal F. The output of decoder gate 73 at terminal Fis applied as one input to the AND gate 61, FIG. 4, so as to gate a TP-2timing pulse through the gate 61 and gate 75, which is being held openby the load command signal applied thereto via OR gate 260, to the setinput of the load flip-flops 57. Setting flip-flop 57 applies a signalto the clear input of the clear flip-flop 56 thereby resetting the clearflipflop to remove the clear signal from its terminal A and from theline 62. Removing the clear signal from line 62 activates the loadterminal LD of the counter 55 which in turn renders the CT terminalinactive to stop further counting by the counter 55 and at the same timerenders the four bit data input terminals to counter 55 effective. Atthis time the counter 55 acts as a unity gain amplifier wherein thebinary signal appearing on its data input terminals from bit lines 3 to6 of bus 22 are amplified and appear as the addressing inputs to each ofthe four chips 30 to 33 in parallel. At the time the load flip-flop 57is set via gates 61 and 75, its activated output 60 opens the set inputgate 76 of the data request flip-flop 58. The latter gate, gates a TP-6timing pulse to the set input of the data request flip-flop 58. Whenflip-flop 58 is set the output line 78 and terminal B becomes active. Atthis time the active output 78 of the data request flip-flop 58 isapplied as shown in FIG. I to the printer control circuits 11. Thelatter device responds to the activation of the control signal 78 tosend a data request to the central processor 10. The central processorin turn sends back the first signal byte comprising the coded charactersto be stored in the buffer memory 14. As the central processor 10returns the coded signal byte to the output data register of the printercontrol circuits 11 and hence to the output data bus 22, the controlcircuits ll responds to the receipt of a data byte by activating line79. The

control signal so developed on line 79 is applied to a clear input gate79a of the data request flip-flop, FIG. 4, to in turn gate a TP-l timingpulse through to the clear input of the data request flip-flop 58 toclear this flip-flop and to remove the output 78 from its activecondition. When the requested data appears on bus 22 all 8 of its bitsserve to address the corresponding location of the associative memory.Bits 7 and 8 are de coded by the four gates which are represented at 39and 42 of FIG. 5 to activate the appropriate chip select terminal 35through 38. Bits 3 through 6 of the received coded signal byte areapplied through the data terminals of counter 55 to the addressterminals of the four chips to effect a word selection within the fourchips. Bits l and 2 are decoded by the four gates represented at 48 and49, FIG. 5, to provide bit selection of the selected word in theselected chip. In this latter context the output of each of the fourgates represented by gates 48 and 49 is applied through the respectiveOR gate 480 and 49a to the one input of each of the respective AND gatesshown at 48b and 49b to the set input terminals of the data inputflip-flops represented at 67 and 68. The l and 2 bits of the receiveddata byte on the bus 22 will be decoded by gats 4849 to open one of thefour gates 48b 49b and thereby gate a TP-4 timing pulse to the set inputterminal of one of four flipflops 67-68. Gate 82 in the write enablecircuit is new active and gate 7] inactive. Gate 82 will therefore gatea TP-S pulse through buffer 70 to the write enable line 70a to cause abinary one to be written into the bit position selected by flip-flop67-68. Then at TP-6 following the storage of a binary one in theselected bit position of the selected word of the selected chip, thedata request flip-flop 58 is again set by a TP-6 passing through gate 76to make the next data request. Then at TP-l following receipt of thenext byte, the data flip-flop 58 is cleared by gate 79a. Clearingflip-flop 58 renders gate 82 effective to pass the next TP-S through ORgate 70 to activate the write enable circuit and thus store a binary onein the next addressed bit position of the selected word and chip. Thisaction continues until the printer control ll detects (such as by acounter) that all of the code bytes have been received from theprocessor. At that time the printer control ll places a signal on lineto clear the load flipflop 57 and thus block gate 76 terminating theload operation.

A characteristic of the memory chips 30-33 is that the writing isdestructive, so that upon energization of the write enable (WE) circuitsall four bits of the selected word in the selected chip will store thebinary condition present in the four associated input flip-flops. Thusto prevent the destruction of the unselected three bits of a selectedword, the output bit from each bit position of a chip is fed backthrough corresponding lines shown as lines -91 for chip 30 and buffers48a to 49a to the set input gates 48b to 49b. In operation then, at TP-3each of the input flip-flops 67-68 is cleared to zero by the TP-3applied to the reset input OR gates, 65-66. At TP-4 each of the setinput gates 48b-49b is strobed to set each of the unselected flip-flops67 and 68 to the state previously stored in the corresponding bitposition of the memory as fed back via lines 90 to 91 and while theselected bit position is set to binary one via the decode gates 4849.Then at TP-S the write enable circuit (WE) is rendered operative viagate 82 to store the conditions of all four flip-flops 67-68 back intothe selected word of the selected chip.

After the memory 13 has been cleared and then set by the load command asdescribed above, the central processor issues the print command. Theprint command when recieved by the control circuits 11 causes theactivation of control lines 27 and 80. Activating these two lines setsthe load flip-flop 57 via gate 92. Setting the load flip-flop 57conditions the setting of the data request flip-flop 58 via gate 76.This flip-flop is set at TP-6 via gate 76 and then reset at TP-l viagate 790. Each setting of the data request flip-flop causes a byte ofdata to be transmitted from the central processor 10 to the controlcircuits 11. This time, however, the bytes that are transmitted arethose forming a line of data to be printed. Finally, after apredetermined number of such bytes are transmitted, the control circuit11 deactivates line 80 to clear the load flip-flop 57 and cause thecessation of further data requests.

As each byte of print data is received and applied via bus 22 to theaddressing circuit of the associative memory 13 it reads out the bitstored in the addressed location in the manner previously described inconnection with FIG. 1. Specifically, bits 7 and 8 select the chip forread out; bits 3 to 6 select the word in the chip and bits I and 2select the bit position of the word being read out. To select the bitposition of the selected words, bits I and 2 are decoded by the fourgates represented at 48 and 49 to energize one of the terminals R to U(FIG. 5) thus opening one of the four output gates repre sented at 45and 46 (FIG. 3). The output of these four gates are applied to the ORgate 47 so that as each bit is read out of the memory it passes throughthe OR GATE 47. The binary zeros read out are inverted at the output ofOR gate 47 as indicated by the small circle at the output of this ORgate and applied to AND gate 470. This gate also has impressed thereonthe control signals from control lines 27 and 80 which are both ac tiveduring the time that the print data bytes are being transmitted. Alsoapplied to this gate is the output line 78 of the data request flip-flop58. This line becomes inactive at TP-l following receipt of a data byteand stays inactive until TP-b. Thus during this period a binary zeroread out of the memory is gated through gate 47a to line 23a where itappears as a decrementing pulse for the comparison match counter 19(FIG. 1).

In the operation of the printer, it will frequently occur that the codeutilized by the printer will call for the printing of capital letters,for instance, while the type carrier will have only lower case letterscarried thereby or vice versa. In certain codes the distinction betweenupper and lower case letters is represented by different combinations ofthe 7th and 8th bits. The re maining six bits for a capital and a lowercase letter is represented by identical code combinations. When thisoccurs the programmer can elect to have the printer print the availableprint characters (upper or lower case) irrespective of the bitcombinations used for the 7th and 8th bit positions by issuing a foldcommand. In this case, the fold command follows the *load" command andprecedes the print command. When the fold command is recieved by thecontrol circuits ll of the printer it causes the activation of line 81from the control circuit 11 which in turn enables gate 93 (FIG. 5). Thenwhen the print command is received it causes the activation of line 27to apply a chip select signal via the four OR gates 39a to 420 to allthe chip select terminals 35 to 38 thereby activating all of the chips.Then on read out the corresponding bit location of all four chips willbe read out and any one of the four locations storing a one will berecognized as containing a printable location. Conversely, if all of thefour locations being read out store a zero, this condition will berecognized as a non-printable and it will cause the counter 19 to bedecremented.

From the foregoing description it will be seen that a singleconventional load command operates to automatically and simultaneouslyload the code buffer and set the associative memory so that on issuanceof the print command the printable and non-printable characters areaccounted for automatically as they are stored in the print buffer.

What is claimed is:

1. In a high speed printer system which includes a moving type memberhaving a predetermined number of different type characters carriedthereby, a code buffer memory for storing a multi-bit binary codedrepresentation of each character on the type member, and a print linebuffer memory for storing multi-bit binary coded representations of thecharacters to be printed; the improvement which comprises: anassociative memory having a set of addressing input terminals and atleast as many one bit storage locations as there are differentcharacters to be printed by the system, means for initially setting eachof the storage locations in said associative memory to store a firstbinary bit, means storing a set of coded signal representations in saidcode buffer, said set representing the characters on said type member,means for simultaneously applying the coded signal representationscomprising said set to the addressing input terminals of saidassociative memory to cause each storage location in said associativememory addressed by said coded signal representations to store a secondbinary bit, means storing a set of data characters in the print linebuffer memory, means simultaneously applying the set of data charactersto the addressing input terminals of said associative memory to causethe binary bits stored in the storage locations being addressed by thedata characters to be read out from the associative buffer, and countingmeans for counting the number of first bits read out from saidassociative memory.

2. The system of claim 1 wherein said associative memory has as manystorage locations as there are possible code combinations in themulti-bit binary code utilized by the system.

3. The system of claim I wherein means are provided to permit differentdata characters codes to address the same associative memory location.

e system of claim 3 wherein the last-named means may be selectivelyrendered operative.

5. The system of claim 1 wherein means are provided to permit a singledata character to address a plurality of locations in said associativememory.

6. The system of claim 5 wherein the last-named means may be selectivelyrendered operative.

7. The system of claim 1 wherein the associative memory is made up of aplurality of similar memory sections and each of said sections includesa first decoder responsive to a first portion of a coded addressingsignal to select a corresponding location in each of said sections and asecond decoder means responsive to a second portion of the addressingsignal to select one of the sections.

8. The system of claim 7 wherein means are provided to by-pass thesecond decoder means.

9. The system of claim 8 wherein the by-pass means may be selectivelyrendered operative.

1. In a high speed printer system which includes a moving type memberhaving a predetermined number of different type characters carriedthereby, a code buffer memory for storing a multi-bit binary codedrepresentation of each character on the type member, and a print linebuffer memory for storing multi-bit binary coded representations of thecharacters to be printed; the improvement which comprises: anassociative memory having a set of addressing input terminals and atleast as many one bit storage locations as there are differentcharacters to be printed by the system, means for initially setting eachof the storage locations in said associative memory to store a firstbinary bit, means storing a set of coded signal representations in saidcode buffer, said set representing the characters on said type member,means for simultaneously applying the coded signal representationscomprising said set to the addressing input terminals of saidassociative memory to cause each storage location in said associativememory addressed by said coded signal representations to store a secondbinary bit, means storing a set of data characters in the print linebuffer memory, means simultaneously applying the set of data charactersto the addressing input terminals of said associative memory to causethe binary bits stored in the storage locations being addressed by thedata characters to be read out from the associative buffer, and countingmeans for counting the number of first bits read out from saidassociative memory.
 2. The system of claim 1 wherein said associativememory has as many storage locations as there are possible codecombinations in the multi-bit binary code utilized by the system.
 3. Thesystem of claim 1 wherein means are provided to permit different printcharacter codes to address the same associative memory location.
 4. Thesystem of claim 3 wherein the last-named means may be selectivelyrendered operative.
 5. The system of claim 1 wherein means are providedto permit a single print character code to address a plurality oflocations in said associative memory.
 6. The system of claim 5 whereinthe last-named means may be selectively rendered operative.
 7. Thesystem of claim 1 wherein the associative memory is made up of aplurality of similar memory sections and each of said sections includesa first decoder responsive to a first portion of a coded addressingsignal to select a corresponding location in each of said sections and asecond decoder means responsive to a second portion of the addressingsignal to select one of the sections.
 8. The system of claim 7 whereinmeans are provided to by-pass the second decoder means.
 9. The system ofclaim 8 wherein the by-pass means may be selectively rendered operative.